An input-output (I/O) receiver is an interface circuit for internal and external signal exchange of an IC chip. The main function of an I/O receiver is to receive digital/analog signals. In some applications, the external voltage may be higher than the internal power supply voltage of the chip. Therefore, a voltage resistant circuit is commonly designed in an I/O receiver in order to protect the I/O receiver.
FIG. 1 shows a schematic view of an existing I/O receiver. Referring to FIG. 1, the receiving terminal receives signals from Port PAD. The voltage level Vin at Port PAD is higher than the power supply voltage VDD1 of the receiver. When the signal at Port PAD is directly transmitted to Node B, a high voltage level may cause reliability issues of NMOS transistors M29 and M30. Therefore, the I/O receiver further includes an NMOS transistor M31 to reduce the maximum level of the voltage signal at Node B.
As shown in FIG. 1, the source electrode of the NMOS transistor M31 is coupled with Port PAD, while the gate electrode of the NMOS transistor M31 is coupled with the power supply voltage VDD1. Thus, the voltage level at Node B is controlled in a range between 0 and a value of (VDD1−Vthn), where Vthn is the threshold voltage of NMOS transistor M31. Therefore, introducing the NMOS transistor M31 into the I/O receiver may provide protection for the NMOS transistor M29 and the NMOS transistor M30. Further, the gate electrode of the PMOS transistor M27 is connected to Port PAD so that leakage current from the power supply voltage VDD1 to ground (i.e. Port VSS) may be avoided. Moreover, the voltage-level converting unit reduces the received voltage signal and converts the received voltage signal into an internal voltage signal. The internal voltage signal is transmitted into the internal chip through Port C.
However, in existing I/O receivers, the maximum value of the voltage signal at Node B is (VDD1−Vthn), which cannot reach the operational power supply voltage VDD1 of the I/O receiver. Therefore, the operation speed of the I/O receiver may be reduced and the performance of the I/O receiver may be degraded.
The disclosed I/O receivers are directed to solve one or more problems set forth above and other problems in the art.